Resistor-based digital to analog converters (DACs) are constructed using a string of like size resistors between an upper and lower reference voltage and a set of muxing devices which selectively connect each node within the resistor network to the DAC output as shown in FIG. 1. The muxing devices 115 of DAC 100 may be a single transistor, a complimentary pair of transistors or other selective coupling device known in the art. DAC 100 includes resistors 105a-105p configured as resistor array series connected between VREF1 and VREF2. Selection gates 115a-115p connect voltage divider nodes 110a-110p to the DAC output, DACOUT. Address inputs 180 to DAC 100 are decoded by address decoder 185 to drive one of select signals 190 which enables one of selection gates 115a-115p to connect the chosen voltage divider node to DACOUT.
As the accuracy, or address bit width of DAC 100 increases, so must the number or resistors 105, voltage divider nodes 110 and selection gates 115 (e.g. multiplexers or muxs). DAC 100 has “P” resistors 105, voltage divider nodes 110 and selection gates 115 where P=2N and N is the number of address bits in DAC 100. For example, a 5 bit DAC 100 will have 32 voltage nodes 110 requiring muxing, an 8 bit DAC 100 will have 256 voltage nodes 110, and a 10 bit DAC 100 has 1024 voltage nodes 110. As the number of voltage nodes 110 increases, the load from the mux devices 115 limits the performance of DAC 100. Therefore, a DAC 100 having an N value larger than 5 is impractical for DAC 100.
To provide higher accuracy DACs and/or higher frequency operation, designers employ a mux hierarchy as shown in DAC hierarchy 200 of FIG. 2. DAC hierarchy 200 also has “P” resistors 205a-205p and “P” voltage divider nodes 210a-210p where “P” is defined 2N and N is the number of address inputs to DAC 200. In a hierarchical system 2N selection gates or mux devices still provide selection of the resistor array via voltage divider nodes 210a-210p, however instead of all mux device outputs being connected to the DAC output, DACOUT, muxs are divided into first hierarchy multiplexor (mux) groups 225a-225q. DAC hierarchy 200 includes “Q” first hierarchy mux groups where “Q” is typically set to a power of 2 equal to or greater than 21. Each first hierarchy mux group 225a-225q contains selection gates or mux devices 220a-220s select 1 of P/Q voltage divider nodes for connection to the output node of their respective first hierarchy output node 230a-230q where the number of first hierarchy mux groups and first hierarchy output nodes is equivalent. The “Q” first hierarchy output nodes output nodes are then multiplexed to the output, or alternatively to another level of hierarchy. Generally, DACs with address spaces of 28 or larger use hierarchical muxing with 3 levels of muxing between the resistor array and the output being common. A DAC with 3 levels of output multiplexer hierarchy is illustrated in FIG. 2.
In illustrated DAC hierarchy 200, first hierarchy output nodes 230a-230q are selectively connected to 2nd hierarchy output nodes 245a-245r through 2nd hierarchy mux groups 240a-240r. Each 2nd hierarchy mux group contains selection gates or mux devices 235a-235t and 2nd hierarchy output nodes 245a-245r are selectively coupled to the output, DACOUT through 3rd hierarchy mux devices 250a-250r. DAC 200 according to FIG. 2 has “R” 2nd hierarchy mux groups, 2nd hierarchy output nodes and 3rd hierarchy mux devices where the value of R is typically set to a power of 2 equal to or greater than 21. The number of selection gates or mux devices 235a-235t in each 2nd hierarchy mux groups is set to “T” where T=Q/R. For example, in DAC 200 the value of N may be 10 yielding 1024 voltage divider nodes. Q and R values of 64 and 8 respectively would yield 64—first hierarchy mux groups 225a-225q each containing 16—first hierarchy selection gates or mux devices 220a-220s and connecting 16 voltage divider nodes to one of 64—first hierarchy output nodes 230a-230q, 8-2nd hierarchy mux groups 240a-240r each containing 8-2nd hierarchy selection gates or mux devices 235a-235t, connecting 8—first hierarchy output nodes to one of 8-2nd hierarchy output nodes 245a-245r, and 8-3rd hierarchy selection gates or mux devices, 250a-250r for selectively connecting one of the 2nd hierarchy output nodes to DACOUT. The mux hierarchy allows a reduction in the capacitance which must be driven to change the DAC output to the voltage of any resistor divider node 210a-210p at the cost of extra mux delay/resistance due the multiple stages of selection gate or mux device which the data must flow through. For the example DAC with N=10, Q=64, R=8, any selected connection path between voltage divider nodes 210a-210p and the output is loaded by only 32 selection gates or mux devices as compared to 1024 mux devices for the DAC of FIG. 1, but the signal would have to propagate through three levels of mux device in series, increasing the resistive load.
Addresses 280 are decoded by address decoder 285 to enable connection of the chosen voltage divider node to DACOUT in DAC 200. Decoder 285 contains units 285a, 285b and 285c, each decoding a portion of address 280 to select the 1st hierarchy selection gates, 2nd hierarchy selection gates and 3rd hierarchy selection gates required to complete the path between the voltage divider node and DACOUT. Select signals 290 are provided for connecting the address decoder to the 1st hierarchy select gates (290a), the 2nd hierarchy select gates (290b) and the 3rd hierarchy select gates (Not Shown)
While hierarchical structures of DAC 200 work well for general purpose DACs in which the digital data pattern driving the DAC inputs is random, the delay imposed by the multiple stages of muxing limits the performance in DACs designed for use within successive approximation analog to digital converters (SARADCs). The reference ranging algorithm applied by the SAR demands the ability to switch across major portions of the address space during reset and the first several patterns of the approximation. What is needed is a resistor DAC node selection architecture which allows for both low output capacitance and low output resistance for performance-limiting addresses in order to maximize DAC performance.